/* linux/include/asm-arm/arch-at91sam9260/at91sam9260_sys.h
 * 
 * Hardware definition for the sys peripheral in the ATMEL at91sam9260 processor
 * 
 * Generated  12/07/2006 (15:04:00) AT91 SW Application Group from SYS_SAM9260 V1.2
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9260_SYS_H
#define __AT91SAM9260_SYS_H

/* -------------------------------------------------------- */
/* SYS ID definitions for  AT91SAM9260           */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* SYS Base Address definitions for  AT91SAM9260   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SYS       	0xFFFFFD00 /**< SYS base address */

/* -------------------------------------------------------- */
/* PIO definition for SYS hardware peripheral */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* Register offset definition for SYS hardware peripheral */
/* -------------------------------------------------------- */
#define SDRAMC_MR 	(0x0000) 	/**< SDRAM Controller Mode Register */
#define SDRAMC_TR 	(0x0004) 	/**< SDRAM Controller Refresh Timer Register */
#define SDRAMC_CR 	(0x0008) 	/**< SDRAM Controller Configuration Register */
#define SDRAMC_HSR 	(0x000C) 	/**< SDRAM Controller High Speed Register */
#define SDRAMC_LPR 	(0x0010) 	/**< SDRAM Controller Low Power Register */
#define SDRAMC_IER 	(0x0014) 	/**< SDRAM Controller Interrupt Enable Register */
#define SDRAMC_IDR 	(0x0018) 	/**< SDRAM Controller Interrupt Disable Register */
#define SDRAMC_IMR 	(0x001C) 	/**< SDRAM Controller Interrupt Mask Register */
#define SDRAMC_ISR 	(0x0020) 	/**< SDRAM Controller Interrupt Mask Register */
#define SDRAMC_MDR 	(0x0024) 	/**< SDRAM Memory Device Register */
#define SMC_SETUP0 	(0x0200) 	/**<  Setup Register for CS 0 */
#define SMC_PULSE0 	(0x0204) 	/**<  Pulse Register for CS 0 */
#define SMC_CYCLE0 	(0x0208) 	/**<  Cycle Register for CS 0 */
#define SMC_CTRL0 	(0x020C) 	/**<  Control Register for CS 0 */
#define SMC_SETUP1 	(0x0210) 	/**<  Setup Register for CS 1 */
#define SMC_PULSE1 	(0x0214) 	/**<  Pulse Register for CS 1 */
#define SMC_CYCLE1 	(0x0218) 	/**<  Cycle Register for CS 1 */
#define SMC_CTRL1 	(0x021C) 	/**<  Control Register for CS 1 */
#define SMC_SETUP2 	(0x0220) 	/**<  Setup Register for CS 2 */
#define SMC_PULSE2 	(0x0224) 	/**<  Pulse Register for CS 2 */
#define SMC_CYCLE2 	(0x0228) 	/**<  Cycle Register for CS 2 */
#define SMC_CTRL2 	(0x022C) 	/**<  Control Register for CS 2 */
#define SMC_SETUP3 	(0x0230) 	/**<  Setup Register for CS 3 */
#define SMC_PULSE3 	(0x0234) 	/**<  Pulse Register for CS 3 */
#define SMC_CYCLE3 	(0x0238) 	/**<  Cycle Register for CS 3 */
#define SMC_CTRL3 	(0x023C) 	/**<  Control Register for CS 3 */
#define SMC_SETUP4 	(0x0240) 	/**<  Setup Register for CS 4 */
#define SMC_PULSE4 	(0x0244) 	/**<  Pulse Register for CS 4 */
#define SMC_CYCLE4 	(0x0248) 	/**<  Cycle Register for CS 4 */
#define SMC_CTRL4 	(0x024C) 	/**<  Control Register for CS 4 */
#define SMC_SETUP5 	(0x0250) 	/**<  Setup Register for CS 5 */
#define SMC_PULSE5 	(0x0254) 	/**<  Pulse Register for CS 5 */
#define SMC_CYCLE5 	(0x0258) 	/**<  Cycle Register for CS 5 */
#define SMC_CTRL5 	(0x025C) 	/**<  Control Register for CS 5 */
#define SMC_SETUP6 	(0x0260) 	/**<  Setup Register for CS 6 */
#define SMC_PULSE6 	(0x0264) 	/**<  Pulse Register for CS 6 */
#define SMC_CYCLE6 	(0x0268) 	/**<  Cycle Register for CS 6 */
#define SMC_CTRL6 	(0x026C) 	/**<  Control Register for CS 6 */
#define SMC_SETUP7 	(0x0270) 	/**<  Setup Register for CS 7 */
#define SMC_PULSE7 	(0x0274) 	/**<  Pulse Register for CS 7 */
#define SMC_CYCLE7 	(0x0278) 	/**<  Cycle Register for CS 7 */
#define SMC_CTRL7 	(0x027C) 	/**<  Control Register for CS 7 */
#define MATRIX_MCFG0 	(0x0400) 	/**<  Master Configuration Register 0 (ram96k)      */
#define MATRIX_MCFG1 	(0x0404) 	/**<  Master Configuration Register 1 (rom)     */
#define MATRIX_MCFG2 	(0x0408) 	/**<  Master Configuration Register 2 (hperiphs)  */
#define MATRIX_MCFG3 	(0x040C) 	/**<  Master Configuration Register 3 (ebi) */
#define MATRIX_MCFG4 	(0x0410) 	/**<  Master Configuration Register 4 (bridge)     */
#define MATRIX_MCFG5 	(0x0414) 	/**<  Master Configuration Register 5 (mailbox)     */
#define MATRIX_MCFG6 	(0x0418) 	/**<  Master Configuration Register 6 (ram16k)   */
#define MATRIX_MCFG7 	(0x041C) 	/**<  Master Configuration Register 7 (teak_prog)      */
#define MATRIX_SCFG0 	(0x0440) 	/**<  Slave Configuration Register 0 (ram96k)      */
#define MATRIX_SCFG1 	(0x0444) 	/**<  Slave Configuration Register 1 (rom)     */
#define MATRIX_SCFG2 	(0x0448) 	/**<  Slave Configuration Register 2 (hperiphs)  */
#define MATRIX_SCFG3 	(0x044C) 	/**<  Slave Configuration Register 3 (ebi) */
#define MATRIX_SCFG4 	(0x0450) 	/**<  Slave Configuration Register 4 (bridge)     */
#define MATRIX_PRAS0 	(0x0480) 	/**<  PRAS0 (ram0)  */
#define MATRIX_PRBS0 	(0x0484) 	/**<  PRBS0 (ram0)  */
#define MATRIX_PRAS1 	(0x0488) 	/**<  PRAS1 (ram1)  */
#define MATRIX_PRBS1 	(0x048C) 	/**<  PRBS1 (ram1)  */
#define MATRIX_PRAS2 	(0x0490) 	/**<  PRAS2 (ram2)  */
#define MATRIX_PRBS2 	(0x0494) 	/**<  PRBS2 (ram2)  */
#define MATRIX_MRCR 	(0x0500) 	/**<  Master Remp Control Register  */
#define CCFG_EBICSA 	(0x051C) 	/**<  EBI Chip Select Assignement Register */
#define MATRIX_TEAKCFG 	(0x052C) 	/**<  Slave 7 (teak_prog) Special Function Register */
#define CCFG_MATRIXVERSION 	(0x05FC) 	/**<  Version Register */
#define AIC_SMR 	(0x0600) 	/**< Source Mode Register */
#define AIC_SVR 	(0x0680) 	/**< Source Vector Register */
#define AIC_IVR 	(0x0700) 	/**< IRQ Vector Register */
#define AIC_FVR 	(0x0704) 	/**< FIQ Vector Register */
#define AIC_ISR 	(0x0708) 	/**< Interrupt Status Register */
#define AIC_IPR 	(0x070C) 	/**< Interrupt Pending Register */
#define AIC_IMR 	(0x0710) 	/**< Interrupt Mask Register */
#define AIC_CISR 	(0x0714) 	/**< Core Interrupt Status Register */
#define AIC_IECR 	(0x0720) 	/**< Interrupt Enable Command Register */
#define AIC_IDCR 	(0x0724) 	/**< Interrupt Disable Command Register */
#define AIC_ICCR 	(0x0728) 	/**< Interrupt Clear Command Register */
#define AIC_ISCR 	(0x072C) 	/**< Interrupt Set Command Register */
#define AIC_EOICR 	(0x0730) 	/**< End of Interrupt Command Register */
#define AIC_SPU 	(0x0734) 	/**< Spurious Vector Register */
#define AIC_DCR 	(0x0738) 	/**< Debug Control Register (Protect) */
#define AIC_FFER 	(0x0740) 	/**< Fast Forcing Enable Register */
#define AIC_FFDR 	(0x0744) 	/**< Fast Forcing Disable Register */
#define AIC_FFSR 	(0x0748) 	/**< Fast Forcing Status Register */
#define DBGU_CR 	(0x0800) 	/**< Control Register */
#define DBGU_MR 	(0x0804) 	/**< Mode Register */
#define DBGU_IER 	(0x0808) 	/**< Interrupt Enable Register */
#define DBGU_IDR 	(0x080C) 	/**< Interrupt Disable Register */
#define DBGU_IMR 	(0x0810) 	/**< Interrupt Mask Register */
#define DBGU_CSR 	(0x0814) 	/**< Channel Status Register */
#define DBGU_RHR 	(0x0818) 	/**< Receiver Holding Register */
#define DBGU_THR 	(0x081C) 	/**< Transmitter Holding Register */
#define DBGU_BRGR 	(0x0820) 	/**< Baud Rate Generator Register */
#define DBGU_CIDR 	(0x0840) 	/**< Chip ID Register */
#define DBGU_EXID 	(0x0844) 	/**< Chip ID Extension Register */
#define DBGU_FNTR 	(0x0848) 	/**< Force NTRST Register */
#define DBGU_RPR 	(0x0900) 	/**< Receive Pointer Register */
#define DBGU_RCR 	(0x0904) 	/**< Receive Counter Register */
#define DBGU_TPR 	(0x0908) 	/**< Transmit Pointer Register */
#define DBGU_TCR 	(0x090C) 	/**< Transmit Counter Register */
#define DBGU_RNPR 	(0x0910) 	/**< Receive Next Pointer Register */
#define DBGU_RNCR 	(0x0914) 	/**< Receive Next Counter Register */
#define DBGU_TNPR 	(0x0918) 	/**< Transmit Next Pointer Register */
#define DBGU_TNCR 	(0x091C) 	/**< Transmit Next Counter Register */
#define DBGU_PTCR 	(0x0920) 	/**< PDC Transfer Control Register */
#define DBGU_PTSR 	(0x0924) 	/**< PDC Transfer Status Register */
#define PIOA_PER 	(0x0A00) 	/**< PIO Enable Register */
#define PIOA_PDR 	(0x0A04) 	/**< PIO Disable Register */
#define PIOA_PSR 	(0x0A08) 	/**< PIO Status Register */
#define PIOA_OER 	(0x0A10) 	/**< Output Enable Register */
#define PIOA_ODR 	(0x0A14) 	/**< Output Disable Registerr */
#define PIOA_OSR 	(0x0A18) 	/**< Output Status Register */
#define PIOA_IFER 	(0x0A20) 	/**< Input Filter Enable Register */
#define PIOA_IFDR 	(0x0A24) 	/**< Input Filter Disable Register */
#define PIOA_IFSR 	(0x0A28) 	/**< Input Filter Status Register */
#define PIOA_SODR 	(0x0A30) 	/**< Set Output Data Register */
#define PIOA_CODR 	(0x0A34) 	/**< Clear Output Data Register */
#define PIOA_ODSR 	(0x0A38) 	/**< Output Data Status Register */
#define PIOA_PDSR 	(0x0A3C) 	/**< Pin Data Status Register */
#define PIOA_IER 	(0x0A40) 	/**< Interrupt Enable Register */
#define PIOA_IDR 	(0x0A44) 	/**< Interrupt Disable Register */
#define PIOA_IMR 	(0x0A48) 	/**< Interrupt Mask Register */
#define PIOA_ISR 	(0x0A4C) 	/**< Interrupt Status Register */
#define PIOA_MDER 	(0x0A50) 	/**< Multi-driver Enable Register */
#define PIOA_MDDR 	(0x0A54) 	/**< Multi-driver Disable Register */
#define PIOA_MDSR 	(0x0A58) 	/**< Multi-driver Status Register */
#define PIOA_PPUDR 	(0x0A60) 	/**< Pull-up Disable Register */
#define PIOA_PPUER 	(0x0A64) 	/**< Pull-up Enable Register */
#define PIOA_PPUSR 	(0x0A68) 	/**< Pull-up Status Register */
#define PIOA_ASR 	(0x0A70) 	/**< Select A Register */
#define PIOA_BSR 	(0x0A74) 	/**< Select B Register */
#define PIOA_ABSR 	(0x0A78) 	/**< AB Select Status Register */
#define PIOA_OWER 	(0x0AA0) 	/**< Output Write Enable Register */
#define PIOA_OWDR 	(0x0AA4) 	/**< Output Write Disable Register */
#define PIOA_OWSR 	(0x0AA8) 	/**< Output Write Status Register */
#define PIOB_PER 	(0x0C00) 	/**< PIO Enable Register */
#define PIOB_PDR 	(0x0C04) 	/**< PIO Disable Register */
#define PIOB_PSR 	(0x0C08) 	/**< PIO Status Register */
#define PIOB_OER 	(0x0C10) 	/**< Output Enable Register */
#define PIOB_ODR 	(0x0C14) 	/**< Output Disable Registerr */
#define PIOB_OSR 	(0x0C18) 	/**< Output Status Register */
#define PIOB_IFER 	(0x0C20) 	/**< Input Filter Enable Register */
#define PIOB_IFDR 	(0x0C24) 	/**< Input Filter Disable Register */
#define PIOB_IFSR 	(0x0C28) 	/**< Input Filter Status Register */
#define PIOB_SODR 	(0x0C30) 	/**< Set Output Data Register */
#define PIOB_CODR 	(0x0C34) 	/**< Clear Output Data Register */
#define PIOB_ODSR 	(0x0C38) 	/**< Output Data Status Register */
#define PIOB_PDSR 	(0x0C3C) 	/**< Pin Data Status Register */
#define PIOB_IER 	(0x0C40) 	/**< Interrupt Enable Register */
#define PIOB_IDR 	(0x0C44) 	/**< Interrupt Disable Register */
#define PIOB_IMR 	(0x0C48) 	/**< Interrupt Mask Register */
#define PIOB_ISR 	(0x0C4C) 	/**< Interrupt Status Register */
#define PIOB_MDER 	(0x0C50) 	/**< Multi-driver Enable Register */
#define PIOB_MDDR 	(0x0C54) 	/**< Multi-driver Disable Register */
#define PIOB_MDSR 	(0x0C58) 	/**< Multi-driver Status Register */
#define PIOB_PPUDR 	(0x0C60) 	/**< Pull-up Disable Register */
#define PIOB_PPUER 	(0x0C64) 	/**< Pull-up Enable Register */
#define PIOB_PPUSR 	(0x0C68) 	/**< Pull-up Status Register */
#define PIOB_ASR 	(0x0C70) 	/**< Select A Register */
#define PIOB_BSR 	(0x0C74) 	/**< Select B Register */
#define PIOB_ABSR 	(0x0C78) 	/**< AB Select Status Register */
#define PIOB_OWER 	(0x0CA0) 	/**< Output Write Enable Register */
#define PIOB_OWDR 	(0x0CA4) 	/**< Output Write Disable Register */
#define PIOB_OWSR 	(0x0CA8) 	/**< Output Write Status Register */
#define PIOC_PER 	(0x0E00) 	/**< PIO Enable Register */
#define PIOC_PDR 	(0x0E04) 	/**< PIO Disable Register */
#define PIOC_PSR 	(0x0E08) 	/**< PIO Status Register */
#define PIOC_OER 	(0x0E10) 	/**< Output Enable Register */
#define PIOC_ODR 	(0x0E14) 	/**< Output Disable Registerr */
#define PIOC_OSR 	(0x0E18) 	/**< Output Status Register */
#define PIOC_IFER 	(0x0E20) 	/**< Input Filter Enable Register */
#define PIOC_IFDR 	(0x0E24) 	/**< Input Filter Disable Register */
#define PIOC_IFSR 	(0x0E28) 	/**< Input Filter Status Register */
#define PIOC_SODR 	(0x0E30) 	/**< Set Output Data Register */
#define PIOC_CODR 	(0x0E34) 	/**< Clear Output Data Register */
#define PIOC_ODSR 	(0x0E38) 	/**< Output Data Status Register */
#define PIOC_PDSR 	(0x0E3C) 	/**< Pin Data Status Register */
#define PIOC_IER 	(0x0E40) 	/**< Interrupt Enable Register */
#define PIOC_IDR 	(0x0E44) 	/**< Interrupt Disable Register */
#define PIOC_IMR 	(0x0E48) 	/**< Interrupt Mask Register */
#define PIOC_ISR 	(0x0E4C) 	/**< Interrupt Status Register */
#define PIOC_MDER 	(0x0E50) 	/**< Multi-driver Enable Register */
#define PIOC_MDDR 	(0x0E54) 	/**< Multi-driver Disable Register */
#define PIOC_MDSR 	(0x0E58) 	/**< Multi-driver Status Register */
#define PIOC_PPUDR 	(0x0E60) 	/**< Pull-up Disable Register */
#define PIOC_PPUER 	(0x0E64) 	/**< Pull-up Enable Register */
#define PIOC_PPUSR 	(0x0E68) 	/**< Pull-up Status Register */
#define PIOC_ASR 	(0x0E70) 	/**< Select A Register */
#define PIOC_BSR 	(0x0E74) 	/**< Select B Register */
#define PIOC_ABSR 	(0x0E78) 	/**< AB Select Status Register */
#define PIOC_OWER 	(0x0EA0) 	/**< Output Write Enable Register */
#define PIOC_OWDR 	(0x0EA4) 	/**< Output Write Disable Register */
#define PIOC_OWSR 	(0x0EA8) 	/**< Output Write Status Register */
#define PMC_SCER 	(0x1200) 	/**< System Clock Enable Register */
#define PMC_SCDR 	(0x1204) 	/**< System Clock Disable Register */
#define PMC_SCSR 	(0x1208) 	/**< System Clock Status Register */
#define PMC_PCER 	(0x1210) 	/**< Peripheral Clock Enable Register */
#define PMC_PCDR 	(0x1214) 	/**< Peripheral Clock Disable Register */
#define PMC_PCSR 	(0x1218) 	/**< Peripheral Clock Status Register */
#define PMC_MOR 	(0x1220) 	/**< Main Oscillator Register */
#define PMC_MCFR 	(0x1224) 	/**< Main Clock  Frequency Register */
#define PMC_PLLAR 	(0x1228) 	/**< PLL A Register */
#define PMC_PLLBR 	(0x122C) 	/**< PLL B Register */
#define PMC_MCKR 	(0x1230) 	/**< Master Clock Register */
#define PMC_PCKR 	(0x1240) 	/**< Programmable Clock Register */
#define PMC_IER 	(0x1260) 	/**< Interrupt Enable Register */
#define PMC_IDR 	(0x1264) 	/**< Interrupt Disable Register */
#define PMC_SR 	(0x1268) 	/**< Status Register */
#define PMC_IMR 	(0x126C) 	/**< Interrupt Mask Register */
#define RSTC_RCR 	(0x1300) 	/**< Reset Control Register */
#define RSTC_RSR 	(0x1304) 	/**< Reset Status Register */
#define RSTC_RMR 	(0x1308) 	/**< Reset Mode Register */
#define SHDWC_SHCR 	(0x1310) 	/**< Shut Down Control Register */
#define SHDWC_SHMR 	(0x1314) 	/**< Shut Down Mode Register */
#define SHDWC_SHSR 	(0x1318) 	/**< Shut Down Status Register */
#define RTTC_RTMR 	(0x1320) 	/**< Real-time Mode Register */
#define RTTC_RTAR 	(0x1324) 	/**< Real-time Alarm Register */
#define RTTC_RTVR 	(0x1328) 	/**< Real-time Value Register */
#define RTTC_RTSR 	(0x132C) 	/**< Real-time Status Register */
#define PITC_PIMR 	(0x1330) 	/**< Period Interval Mode Register */
#define PITC_PISR 	(0x1334) 	/**< Period Interval Status Register */
#define PITC_PIVR 	(0x1338) 	/**< Period Interval Value Register */
#define PITC_PIIR 	(0x133C) 	/**< Period Interval Image Register */
#define WDTC_WDCR 	(0x1340) 	/**< Watchdog Control Register */
#define WDTC_WDMR 	(0x1344) 	/**< Watchdog Mode Register */
#define WDTC_WDSR 	(0x1348) 	/**< Watchdog Status Register */
#define SYS_GPBR0 	(0x1350) 	/**< General Purpose Register 0 */
#define SYS_GPBR1 	(0x1354) 	/**< General Purpose Register 1 */
#define SYS_GPBR2 	(0x1358) 	/**< General Purpose Register 2 */
#define SYS_GPBR3 	(0x135C) 	/**< General Purpose Register 3 */

/* -------------------------------------------------------- */
/* Bitfields definition for SYS hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register GPBR */
/* --- Register GPBR */
/* --- Register GPBR */
/* --- Register GPBR */

#endif /* __AT91SAM9260_SYS_H */
